A semiconductor manufacturer engaged Triple Crown Consulting to migrate a legacy RF and mixed-signal product portfolio to a new foundry process. The assignment combined circuit migration with an ambitious consolidation objective: support multiple existing products on one configurable die while preserving pin-for-pin compatibility, software behavior, and published performance requirements.
| Legacy Portfolio | Foundry Transition | Consolidation Objective |
|---|---|---|
| 9 existing dies in scope | Tower Jazz 180 nm to Global Foundries 180 nm CMOS | One configurable die supporting multiple product variants |
The Migration Challenge
The portfolio combined frequency synthesizers, voltage-controlled oscillators, mixers, I/Q modulators, analog support circuits, and digital control logic. Each product carried its own pinout, configuration, and datasheet requirements. A common die had to accommodate those differences without forcing customers to redesign their boards or rewrite their control software.
The legacy design package also lacked complete system requirements, block specifications, review records, and clean shared block databases. Moving between foundries required attention to device models, passive components, layout rules, and parasitics, even though the nominal process node remained unchanged.
The Triple Crown Engineering Approach
Triple Crown organized the work across RFIC and analog design, digital RTL, mixed-signal verification, and physical design under a common technical lead. The migration plan connected product compatibility requirements to circuit-level decisions, and the verification needed before physical implementation could advance. The migration plan focused on four key activities:
- Recover the design baseline and translate product datasheets into block requirements and a specification compliance matrix.
- Use critical-block feasibility work to assess differences between the source and target processes before expanding the migration.
- Align schematic, layout, and verification of engineers around a shared design database, with explicit checks for connectivity and netlisting readiness.
- Review circuit performance and single-die feasibility as the architecture, floorplan, and verification plan develop.
Early Progress
Triple Crown migrated selected key blocks for feasibility assessment. That work informed a Phase 2 plan addressing the remaining schematic migration, database cleanup, critical-circuit reviews, digital interface readiness, and full-chip verification preparation. It gave the program a concrete basis for identifying the engineering work required before broader implementation.
Engineering Scope and Client Value
Coordinating circuit behavior with digital control and physical implementation.
Triple Crown’s scope extended from legacy design recovery through tapeout preparation. The workstreams below show how the program tied migration tasks to the client’s compatibility and performance objectives.
| Workstream | Engineering Scope | Purpose |
|---|---|---|
| RF and analog circuits | Migrate VCOs, mixers, fractional-N PLLs, bandgap circuits, LDOs, crystal oscillators, and associated analog functions. | Preserve required RF behavior and analog operating conditions in the target process. |
| Simulation and modeling | Plan PVT, Monte Carlo, and noise simulations, inductor EM analysis, package and external-component modeling, and post-layout checks. | Evaluate process sensitivity, variation, noise, and parasitic effects against product specifications. |
| Digital control | Migrate RTL and serial-interface logic, verify register read/write behavior, and address synthesis, timing, DFT planning, and place-and-route readiness. | Maintain software-facing behavior and prepare the digital subsystem for chip integration. |
| Mixed-signal verification | Develop behavioral models, configuration netlists, test cases, and full-chip testbenches for power-up/down and clock-enable sequences. | Check interactions between digital controls and analog blocks across operating configurations. |
| Physical design | Address floorplanning, RF and analog layout, digital implementation, pad-ring and ESD requirements, wire bonding, DRC/LVS, and parasitic extraction. | Connect electrical requirements to a manufacturable implementation and the evidence needed for tapeout review. |
A Coordinated Migration Program
The delivery model placed design and verification work within the client’s engineering environment, using Cadence design, simulation, and implementation tools. Defined phase reviews, a specification compliance matrix, and tracked technical risks provided a framework for evaluating progress and resolving issues across disciplines. Planned deliverables included review packages, migrated design data, verification results, physical design documentation, and the tapeout database.
Relevance to IC, ASIC, and SoC Migration
This RFIC engagement illustrates the breadth of engineering a foundry transition can require. For IC, ASIC, and SoC programs with analog or RF content, the same disciplines help teams evaluate legacy IP reuse, preserve external interfaces, validate changes in process-dependent behavior, and coordinate digital and custom implementation. The common-die objective also demonstrates how migration planning can incorporate product-family consolidation.
Plan Your Migration With Triple Crown
Engage Triple Crown to assess your legacy design package, define compatibility requirements, and build a migration plan around your target process and product priorities. Our engineering services bring specialized circuit, verification, and implementation expertise together with technical program leadership.