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Years of experience: 18 years
Noteworthy project: Noteworthy Project: FPGA Design engineer with Xilinx Zynq, Ultrascale, Kintex, and Vivado experience and has worked on AXI, Ethernet, PCIe, DDR4, and Network Cards.
Years of experience: 36 years
Noteworthy project: Noteworthy Project: Created a test plan for functional and structural verification. Responsible for creating assertion based functional coverage simulation environment.
Years of experience: 21 years
Noteworthy project: Circuit board designer working on DDR PHY of DDRIO/MSIP circuits directly involved in delivering next-generation PHY designs for SoCs and involved in leading-edge CMOS process technology nodes at 10nm, 7nm and beyond.